1. Field of the Invention
The present invention generally relates to error detecting and/or correcting schemes for digital computers and, more particularly, to an error correcting code (ECC) function especially useful for memory systems in personal computers (PCs) and to a parity interface scheme providing a translation capability between the ECC and parity protocols.
2. Description of the Prior Art
Data integrity and system reliability are major concerns for all computer systems. Consequently, various schemes have been developed to insure acceptable levels of error detection and/or correction of data. Parity bits, for example, may be used to detect a single bit error occurring in a finite number of data bits. Various data integrity schemes are particularly appropriate for specific applications in a computer system. For example, error correcting code (ECC) schemes are quite useful for interfacing with memory due to their correction capability coupled with the higher probability of error associated with semiconductor memory. ECC schemes have been used in mainframe computer systems for some time.
As the need for increased data integrity has developed, small systems such as personal computers (PCs) have turned to a stand-alone error correcting code (ECC) function to replace parity schemes in storing and retrieving data from memory. ECC affords the additional protection of single (or more) error correction and multiple error detection by adding a number of check bits to the data before storing it in memory. These check bits, along with the data bits, are decoded after reading from memory to provide the enhanced data integrity.
Existing methods for an ECC buffer to memory provide check bit generation and checking on a large data word which is generally thirty-two bits. However, many components in PCs are only capable of sending or receiving 8-bit or 16-bit units of data, and even 32-bit microprocessors typically do not communicate with memory in 32-bit segments. It is therefore necessary to write words of varying 8-bit or byte lengths while maintaining the integrity of the associated check bits.
In a 32-bit ECC scheme, the check bits that are stored with the data are generated based on the entire thirty-two bits. This makes it necessary to regenerate all of the check bits if even one data bit has changed. Thus, if one byte of data needs to be written to memory, the entire 4-byte double word must first be read, checked and corrected, the new eight bits substituted, and then all four bytes must be rewritten to memory with the appropriate new check bits. The same is true if two or three bytes of data need to be written to memory. This is called a partial write or a read/modify/write operation.
U.S. Pat. No. 4,884,271 to Concha et al. describes a method for handling the read/modify/write problem which uses a correct-on-error scheme where check bits are generated on uncorrected data and then regenerated if the data is found to be in error. This requires a "long" and a "short" read/modify/write cycle, as well as two types of read cycles, to handle data with or without errors, respectively. This approach suffers from being relatively complex in operation. Moreover, the correct-on-error scheme allows data processing to begin while the ECC logic determines if an error is present. This has a disadvantage in that the processor must back up and discard the corrupt data when an error occurs.
U.S. Pat. No. 4,319,356 to Kocol et al. describe a memory that periodically checks and scrubs errors from itself. Kocol et al. do not address the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes.
U.S. Pat. No. 4,852,100 to Christensen et al. describes an error correction and detection method which, like the Concha et al. patent, also incorporates a correct-on-error scheme with multiple ECC sub-blocks. Christensen et al., like Kocol et al., do not address the problems of interfacing memory with a variety of other components that may communicate in words composed of different numbers of bytes. In addition, Christensen et al. use a single ECC unit to handle data of varying numbers of bytes. Column 5 of the Christensen et al. patent describes the dedication of an ECC unit to each sub-block of data for various reasons. While the Christensen et al. approach could be employed to address the problem of storing words of varying numbers of bytes, it is generally not feasible due to the excessive overhead on the number of bit paths and consequently cost and space.
Although an ECC function may be implemented for reading and writing to memory, many computer systems, especially PCs, use parity checking in other applications, most notably the system bus. When more than one integrity protocol is used within a system, an interface must provide translation capability between the different protocols. Typically, such an interface requires separate parity and ECC Exclusive OR (XOR) trees, resulting in signal delay and using valuable silicon real estate.